MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 63

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Table 4-24 Programmable Interval Timer 2 Registers Address Map (Continued)
PIT2_CNTR
DAC0_CTRL
DAC0_DATA
DAC0_STEP
DAC0_MINVAL
DAC0_MAXVAL
DAC1_CTRL
DAC1_DATA
DAC1_STEP
DAC1_MINVAL
DAC1_MAXVAL
CMPA_CTRL
CMPA_STAT
CMPA_FILT
CMPB_CTRL
CMPB_STAT
CMPB_FILT
Register Acronym
Register Acronym
Register Acronym
Register Acronym
Register Acronym
Table 4-25 Digital-to-Analog Converter 0 Registers Address Map
Table 4-26 Digital-to-Analog Converter 0 Registers Address Map
Table 4-27 Comparator A Registers Address Map
Table 4-28 Comparator B Registers Address Map
Address Offset
Address Offset
Address Offset
Address Offset
Address Offset
56F8037/56F8027 Data Sheet, Rev. 7
(CMPA_BASE = $00 F1E0)
(CMPB_BASE = $00 F1F0)
(DAC0_BASE = $00 F1C0)
(DAC1_BASE = $00 F1D0)
(PIT2_BASE = $00 F1B0)
$2
$0
$1
$2
$3
$4
$0
$1
$2
$3
$4
$0
$1
$2
$0
$1
$2
Counter Register
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
Control Register
Status Register
Filter Register
Control Register
Status Register
Filter Register
Register Description
Register Description
Register Description
Register Description
Register Description
Peripheral Memory-Mapped Registers
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