MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 41

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2 Features
The OCCS module interfaces to the oscillator and PLL and offers these features:
The clock generation module provides the programming interface for the PLL, internal relaxation
oscillator, and crystal oscillator.
3.3 Operating Modes
In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be
used to provide a reference clock to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
where:
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.
The 56F8000 family devices’ on-chip clock synthesis module has the following registers:
For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference
Manual.
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Internal relaxation oscillator
Ability to power down the internal relaxation oscillator or crystal oscillator
Ability to put the internal relaxation oscillator into Standby mode
3-bit postscaler provides control for the PLL output
Ability to power down the PLL
Provides a 2X system clock which operates at twice the system clock to the System Integration Module
(SIM)
Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules
Safety shutdown feature is available if the PLL reference clock is lost
Can be driven from an external clock source
Control Register (OCCS_CTRL)
Divide-by Register (OCCS_DIVBY)
Status Register (OCCS_STAT)
Shutdown Register (OCCS_SHUTDN)
Oscillator Control Register (OCCS_OCTRL)
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency x 8) / (postscaler)
postscaler = 1, 2, 4, 8, 16, or 32
56F8037/56F8027 Data Sheet, Rev. 7
Features
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