MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 206
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MC908GR16ACFAE
Manufacturer Part Number
MC908GR16ACFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR16ACFAE.pdf
(270 pages)
Specifications of MC908GR16ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908GR16ACFAE
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC908GR16ACFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI) Module
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
16.11.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, SS is used to select a slave. For CPHA = 0, SS is used to define the start of a transmission. (See
16.4 Transmission
high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of SS from creating a MODF error. See
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If MODFEN is 0 for
an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. When MODFEN is 1, SS is an input-only pin to the SPI regardless of the
state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See
206
A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
MASTER SS
SPE
1. X = Don’t care
MISO/MOSI
SLAVE SS
SLAVE SS
0
1
1
1
CPHA = 0
CPHA = 1
Formats.) Since it is used to indicate the start of a transmission, SS must be toggled
SPMSTR
X
(1))
0
1
1
MODFEN
MC68HC908GR16A Data Sheet, Rev. 1.0
Table
Figure 16-13. CPHA/SS Timing
BYTE 1
Table 16-2. SPI Configuration
X
X
0
1
16-2.
Master without MODF
SPI Configuration
Master with MODF
NOTE
Not enabled
Slave
Figure
BYTE 2
16-13.
16.12.2 SPI Status and Control Register.
16.6.2 Mode Fault Error.)
General-purpose I/O;
General-purpose I/O;
Function of SS Pin
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
BYTE 3
Freescale Semiconductor
For the state of