MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 174

• Manufacturer Part Number: MC908GR16ACFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
The SIM is responsible for:
Table 15-1
174
Addr.
$FE00
$FE01
$FE03
$FE04
$FE05
$FE06
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt arbitration
SIM Break Status Register
SIM Reset Status Register
Stop/wait/reset/break entry and recovery
Internal clock control
SIM Break Flag Control
Signal Name
Register Name
shows the internal signal names used in this section.
CGMXCLK
CGMVCLK
CGMOUT
PORRST
Register (SBFCR)
IRST
R/W
Register 1 (INT1)
Register 2 (INT2)
Register 3 (INT3)
IAB
IDB
Interrupt Status
Interrupt Status
Interrupt Status
See page 187.
See page 188.
See page 189.
See page 183.
See page 184.
See page 184.
(SRSR)
(SBSR)
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
Figure 15-2. SIM I/O Register Summary
Table 15-1. Signal Name Conventions
1. Writing a 0 clears SBSW.
MC68HC908GR16A Data Sheet, Rev. 1.0
BCFE
Bit 7
POR
IF14
IF6
R
R
R
R
0
1
0
0
0
0
0
= Unimplemented
IF13
PIN
IF5
R
R
R
R
R
6
0
0
0
0
0
0
COP
IF12
IF20
IF4
R
R
R
R
R
5
0
0
0
0
0
Description
ILOP
IF11
IF19
IF3
R
R
R
R
R
R
4
0
0
0
0
0
= Reserved
ILAD
IF10
IF18
IF2
R
R
R
R
R
3
0
0
0
0
0
MODRST
IF17
IF1
IF9
R
R
R
R
R
2
0
0
0
0
0
Freescale Semiconductor
Note
SBSW
IF16
LVI
IF8
R
R
R
R
1
0
0
0
0
0
0
(1)
Bit 0
IF15
IF7
R
R
R
R
R
0
0
0
0
0
0
0