C8051F34B-GQ Silicon Laboratories Inc, C8051F34B-GQ Datasheet - Page 177

• Manufacturer Part Number: C8051F34B-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F34B-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• On-chip Adc: 17-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1534

The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the
Endpoint0 FIFO.
Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may
force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit
will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a
STALL condition:
16.10.1.Endpoint0 SETUP Transactions
All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, contain-
ing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other
than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data
from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the
Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate
that it has serviced the OUT packet.
16.10.2.Endpoint0 IN Transactions
When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN
requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the
Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is
transmitted successfully. Note that no interrupt will be generated if an IN request is received before firm-
ware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet
size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet
should be of the maximum packet size excluding the last (residual) packet. If the requested data is an inte-
ger multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet
signaling the end of the transfer. Firmware should set the DATAEND bit to ‘1’ after loading into the
Endpoint0 FIFO the last data packet for a transfer.
Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit
Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is
set to ‘1’ if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode.
Endpoint0 will remain in Transmit Mode until any of the following occur:
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above.
The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY
= ‘0’).
1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set
2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to
3. The host sends a packet that exceeds the maximum packet size for Endpoint0.
4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction.
5. Firmware sets the SDSTL bit (E0CSR.5) to ‘1’.
1. USB0 receives an Endpoint0 SETUP or OUT token.
2. Firmware sends a packet less than the maximum Endpoint0 packet size.
3. Firmware sends a zero-length packet.
to ‘1’.
‘1’.
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Rev. 1.3
177