R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 211
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.41
Figure 14.42
Timer RD Interrupt Enable Register i (i = 0 or 1)
Timer RD Counter i (i = 0 or 1)
(b15)
b7 b6 b5 b4
b7
NOTE:
1.
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Feb 29, 2008
b3 b2
Registers TRDIER0 to TRDIER1 in Input Capture Function
Registers TRD0 to TRD1 in Input Capture Function
b1 b0
(b8)
b0
b7
Count the count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
Bit Symbol
TRDIER0
TRDIER1
(b7-b5)
Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
Page 192 of 485
—
(1)
Input capture/compare match
interrupt enable bit A
Input capture/compare match
interrupt enable bit B
Input capture/compare match
interrupt enable bit C
Input capture/compare match
interrupt enable bit D
Overflow /underflow interrupt
enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b0
Symbol
TRD0
TRD1
Address
Bit Name
0144h
0154h
Function
0 : Disable interrupt (IMIA) by the IMFA bit
1 : Enable interrupt (IMIA) by the IMFA bit
0 : Disable interrupt (IMIB) by the IMFB bit
1 : Enable interrupt (IMIB) by the IMFB bit
0 : Disable interrupt (IMIC) by the IMFC bit
1 : Enable interrupt (IMIC) by the IMFC bit
0 : Disable interrupt (IMID) by the IMFD bit
1 : Enable interrupt (IMID) by the IMFD bit
0 : Disable interrupt (OVI) by the OVF bit
1 : Enable interrupt (OVI) by the OVF bit
0147h-0146h
0157h-0156h
Address
After Reset
11100000b
11100000b
Function
0000h to FFFFh
Setting Range
After Reset
0000h
0000h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
—
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