R5F21184SP#U0 Renesas Electronics America, R5F21184SP#U0 Datasheet - Page 282
R5F21184SP#U0
Manufacturer Part Number
R5F21184SP#U0
Description
IC R8C MCU FLASH 16K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/18r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21181DSPU0.pdf
(43 pages)
3.R5F21181DSPU0.pdf
(259 pages)
Specifications of R5F21184SP#U0
Core Size
16-Bit
Program Memory Size
16KB (16K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x1b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
No. Of I/o's
13
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
3
Digital Ic Case Style
SSOP
Supply Voltage Range
2.7V To 5.5V
Embedded Interface Type
UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Rev.2.00 Oct 17, 2005
REJ09B0001-0200
6.1 Instruction Queue Buffer
Chapter 6
R8C/Tiny Series microcomputers have 4-stage (4-byte) instruction queue buffers. If the instruction queue
buffer has free space when the CPU can use the bus, instruction codes are taken into the instruction queue
buffer. This is referred to as “prefetching”. The CPU reads (fetches) the instruction codes from the instruc-
tion queue buffer as it executes a program.
The explanation of the number of cycles in chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that 8-bit data is read or written to the memory without software
wait states. In the following cases, more cycles may be needed than the number of cycles indicated in this
manual:
Note that if prefetch and data access occur at the same time, data access has priority. Also, if more than
three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space and, therefore, does not prefetch instruction code.
Figure 6.1.1 shows an example of starting a read instruction (without software wait).
• If not all of the instruction codes needed by the CPU have been placed in the instruction queue buffer.
• When reading or writing data to an area in which software wait cycles exist.
• When reading or writing 16-bit data from/to the SFR or the internal memory.
Instruction codes are read in until all of the instruction codes required for program execution are avail-
able. Furthermore, the number of read cycles increases in the following case:
The number of read or write cycles increases to match the number of wait cycles incurred.
The memory is accessed twice to read or write one 16-bit data item. Therefore, the number of read or
write cycles increases by one for each 16-bit data item read or written.
(1) The number of read cycles increases to match the number of wait cycles incurred when reading
instruction codes from an area in which software wait cycles exist.
Calculating the Number of Cycles
page 262 of 263
6.1 Instruction Queue Buffer
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