R5F21184SP#U0 Renesas Electronics America, R5F21184SP#U0 Datasheet - Page 277

• Manufacturer Part Number: R5F21184SP#U0
• Description: IC R8C MCU FLASH 16K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/18r

Specifications of R5F21184SP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x1b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• No. Of I/o's: 13
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 2.7V To 5.5V
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
5.6 Multiple Interrupts
Chapter 5
The internal bit states when control has branched to an interrupt routine are as follows:
By setting the interrupt enable flag (I flag) to 1 in the interrupt routine, interrupts can be reenabled so that an
interrupt request that has higher priority than the processor interrupt priority level (IPL) can be acknowl-
edged. Figure 5.6.1 shows how multiple interrupts are handled.
Interrupt requests that have not been acknowledged due to low interrupt priority level are kept pending.
When the IPL is restored by an REIT instruction and the interrupt priority is determined based on the IPL
contents, the pending interrupt request is acknowledged if the following condition is met:
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
pending interrupt request
Interrupt priority level of
Interrupts
page 257 of 263
>
Restored processor interrupt
priority level (IPL)
5.6 Multiple interrupts