C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 41

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Table 5.5. Flash Electrical Characteristics
V
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
V
V
Missing Clock Detector Timeout
Reset Time Delay
Minimum RST Low Time to 
Generate a System Reset
V
V
Flash Size
Endurance
Retention
Erase Cycle Time
Write Cycle Time
V
DD
DD
DD
DD
DD
DD
1. On the 32 kB Flash devices, 1024 bytes at addresses 0x7C00 to 0x7FFF are reserved.
2. See Table 5.4 for the
= 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
RST Threshold (V
RST Threshold (V
Monitor Turn-on Time
Monitor Supply Current
Parameter
Parameter
RST-LOW
RST-HIGH
C8051F550-3, ‘F560-3,
‘F568-9, and ‘F570-1
C8051F554-7, ‘F564-7, and
‘F572-5
125
25 MHz System Clock
25 MHz System Clock
Write/Erase operations
V
RST-HIGH
°
C
)
)
Conditions
VIO = 5 V; IOL = 70 µA
RST = 0.0 V, VIO = 5 V
Time from last system clock
rising edge to reset initiation
V
V
Delay between release of
any reset source and code 
execution at location 0x0000
specification.
DD
DD
= 2.1V
= 2.5 V
Conditions
Rev. 1.1
V
RST-HIGH
20 k
Min
10
28
79
C8051F55x/56x/57x
2
0.7 x V
32768
1.65
2.25
16384
Min
200
200
—
—
—
—
—
—
6
150 k
Typ
30
84
—
—
IO
1
1.75
2.30
Typ
340
250
155
49
60
—
—
—
—
1
Max
125
—
—
45
—
0.3 x V
Max
1.80
2.45
600
600
175
100
115
40
—
—
2
Erase/Write
IO
Units
Bytes
Years
ms
µs
V
Units
mV
µA
µA
µs
µs
µs
µs
V
V
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