C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 233

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

23. UART0
UART0 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “23.1. Baud Rate Generator” on page 233). A received data FIFO
allows UART0 to receive up to three data bytes before data is lost and an overflow occurs.
UART0 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON0, SBRLH0, and
SBRLL0), two are used for data formatting, control, and status functions (SCON0, SMOD0), and one is
used to send and receive data (SBUF0). The single SBUF0 location provides access to both the transmit
holding register and the receive FIFO. Writes to SBUF0 always access the Transmit register. Reads of
SBUF0 always access the first byte of the Receive FIFO; it is not possible to read data from the
Transmit Holding Register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete). If additional bytes are available in the Receive FIFO, the RI0 bit cannot be cleared by software.
23.1. Baud Rate Generator
The UART0 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock
(SYSCLK) and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for
a wide selection of baud rates over many clock frequencies.
The baud rate generator is configured using three registers: SBCON0, SBRLH0, and SBRLL0. The
UART0 Baud Rate Generator Control Register (SBCON0, SFR Definition 23.4) enables or disables the
baud rate generator and selects the prescaler value for the timer. The baud rate generator must be
enabled for UART0 to function. Registers SBRLH0 and SBRLL0 contain a 16-bit reload value for the dedi-
cated 16-bit timer. The internal timer counts up from the reload value on every clock tick. On timer over-
flows (0xFFFF to 0x0000), the timer is reloaded. The baud rate for UART0 is defined in Equation 23.1,
where “BRG Clock” is the baud rate generator’s selected clock source. For reliable UART operation, it is
recommended that the UART baud rate is not configured for baud rates faster than SYSCLK/16.
SYSCLK
SBRLH0
Timer (16-bit)
Baud Rate Generator
SBRLL0
EN
SBCON0
Figure 23.1. UART0 Block Diagram
Overflow
(1, 4, 12, 48)
Pre-Scaler
Rev. 1.1
Data Formatting
Control / Status
Interrupt
UART0
SMOD0
SCON0
C8051F55x/56x/57x
TX Holding
RX FIFO
(3 Deep)
Register
SBUF0
Logic
Logic
RX
TX
Write to SBUF0
Read of SBUF0
TX0
RX0
233