C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 138

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

C8051F55x/56x/57x
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is as follows:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 16.2 for V
monitor reset. See Table 5.4 for complete electrical characteristics of the V
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The
When programming the Flash in-system, the V
highest system reliability, the time the V
(e.g., setting the V
changing it back to the low threshold setting immediately after the Flash write operation).
138
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
output of the un-calibrated internal regulator could be below the high threshold setting of the V
is the case and the V
reset (POR), the MCU will remain in reset until a POR occurs (i.e., V
POR will force the V
output of the internal regulator. The device will then exit reset and resume normal operation. It is for this reason
Silicon Labs strongly recommends that the V
value upon POR).
DD
DD
monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
monitor (VDMEN bit in VDM0CN = 1).
Monitor to the high threshold setting just before the Flash write operation and then
DD
DD
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
Monitor to the low threshold setting which is guaranteed to be below the un-calibrated
monitor is being turned on from a disabled state, it should be enabled before it
Monitor is set to the high threshold setting and if the MCU receives a non-power on
DD
monitor to stabilize (see Table 5.4 for the V
DD
DD
Monitor is set to the high threshold setting should be minimized
monitor and configuring it as a reset source from a disabled
DD
DD
DD
Rev. 1.1
monitor as a reset source before it is enabled and stabi-
Monitor must be set to the high threshold setting. For the
Monitor is always left in the low threshold setting (i.e. default
DD
Monitor will keep the device in reset). A
DD
DD
monitor.
Monitor turn-on time). 
DD
Monitor. If this
DD