MC9S08GT16AMFDE Freescale Semiconductor, MC9S08GT16AMFDE Datasheet - Page 151

IC MCU 16K FLASH 2K RAM 48-QFN

MC9S08GT16AMFDE

Manufacturer Part Number
MC9S08GT16AMFDE
Description
IC MCU 16K FLASH 2K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08GT16AMFDE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, IRSCI, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
39
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
48QFN EP
Family Name
HCS08
Maximum Speed
40 MHz
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
9.5.5
The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some
cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a
trimming procedure is provided that will allow a very accurate source. This section outlines one example
of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
Freescale Semiconductor
Initial conditions:
1) Clock supplied from ATE has 500 µsec duty period
2) ICG configured for internal reference with 4 MHz bus
Example #4: Internal Clock Generator Trim
INCREASES THE FREQUENCY)
(DECREASING ICGTRM
ICGTRM - 128 / (2**n)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
ICGTRM =
n = n + 1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
IS n > 8?
(COUNT = # OF BUS CLOCKS / 4)
DECREASES THE FREQUENCY)
Figure 9-17. Trim Procedure
NO
START TRIM PROCEDURE
INCOMING CLOCK WIDTH
(INCREASING ICGTRM
ICGTRM = $80, n = 1
ICGTRM + 128 / (2**n)
CASE STATEMENT
MEASURE
ICGTRM =
YES
.
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
COUNT = EXPECTED = 500
Internal Clock Generator (S08ICGV4)
Figure 9-17
STORE ICGTRM VALUE
IN NON-VOLATILE
CONTINUE
MEMORY
while the
151

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