C8051F715-GQ Silicon Laboratories Inc, C8051F715-GQ Datasheet - Page 264
![IC 8051 MCU 8K FLASH 48-TQFP](/photos/12/16/121648/c8051f715-gq_sml.jpg)
C8051F715-GQ
Manufacturer Part Number
C8051F715-GQ
Description
IC 8051 MCU 8K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1619
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F715-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F70x/71x
33.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “21.2. Interrupt Register Descriptions” on page 140); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “21.2. Interrupt Register Descriptions” on page 140). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
33.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“28.3. Priority Crossbar Decoder” on page 185 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 33.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 21.7). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “21.2. Interrupt
Register Descriptions” on page 140), facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 21.7).
264
Note: X = Don't Care
TR0
0
1
1
1
GATE0
X
0
1
1
Rev. 1.0
INT0
X
X
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled
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