C8051F715-GQ Silicon Laboratories Inc, C8051F715-GQ Datasheet - Page 161
![IC 8051 MCU 8K FLASH 48-TQFP](/photos/12/16/121648/c8051f715-gq_sml.jpg)
C8051F715-GQ
Manufacturer Part Number
C8051F715-GQ
Description
IC 8051 MCU 8K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1619
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F715-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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24.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
24.3. Suspend Mode
Suspend mode allows a system running from the internal oscillator to go to a very low power state similar
to Stop mode, but the processor can be awakened by certain events without requiring a reset of the device.
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source.
Note that the clock divider bits CLKDIV[2:0] in register CLKSEL must be set to "divide by 1" when entering
Suspend mode.
Suspend mode can be terminated by five types of events, a port match (described in Section “28.5. Port
Match” on page 192), a Timer 3 overflow (described in Section “33.3. Timer 3” on page 278), a comparator
low output (if enabled), a capacitive sense greater-than comparator interrupt, or a device reset event. In
order to run Timer 3 in Suspend mode, the timer must be configured to clock from the external clock
source/8. When Suspend mode is terminated, the device will continue execution on the instruction follow-
ing the one that set the SUSPEND bit. If the wake event (port match or Timer 3 overflow) was configured to
generate an interrupt, the interrupt will be serviced upon waking the device. If Suspend mode is terminated
by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execu-
tion at address 0x0000.
Note: The device will still enter Suspend mode if a wake source is "pending", and the device will not wake on
such pending sources. It is important to ensure that the intended wake source will trigger after the device
enters Suspend mode. For example, if a CS0 conversion completes and the interrupt fires before the device is
in Suspend mode, that interrupt cannot trigger the wake event. Because port match events are level-sensitive,
pre-existing port match events will trigger a wake, as long as the match condition is still present when the
device enters Suspend.
Rev. 1.0
C8051F70x/71x
161
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