MC9S08AC16CBE Freescale Semiconductor, MC9S08AC16CBE Datasheet - Page 136

• Manufacturer Part Number: MC9S08AC16CBE
• Description: IC MCU 8BIT 16K FLASH 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16CBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• Package: 42SPDIP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Internal Clock Generator (S08ICGV4)
8.3.4
8.3.5
136
Reset
Reset
DCOS
Field
Field
FLT
3:0
0
W
W
R
R
ICG Status Register 2 (ICGS2)
ICG Filter Registers (ICGFLTU, ICGFLTL)
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than n
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 8-10. ICG Upper Filter Register (ICGFLTU)
Table 8-5. ICGFLTU Register Field Descriptions
Table 8-4. ICGS2 Register Field Descriptions
Figure 8-9. ICG Status Register 2 (ICGS2)
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
0
0
5
5
unlock
for two consecutive samples and the DCO clock is not static. This bit is
0
0
0
0
4
4
Description
Description
3
0
0
3
0
0
0
0
2
2
FLT
Freescale Semiconductor
0
0
0
1
1
DCOS
0
0
0
0