MC908JL16CFJE Freescale Semiconductor, MC908JL16CFJE Datasheet - Page 111

• Manufacturer Part Number: MC908JL16CFJE
• Description: IC MCU 16K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4 Functional Description
The Multi-master IIC (MMIIC) Interface is designed for internal serial communication between the MCU
and other IIC devices. The interface uses 2 pins, SCL and SDA for clocking and serial data.
8.4.1 IIC Protocol
The IIC bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All
devices connected to it must have open drain or open collector outputs. Logic AND function is exercised
on both lines with external pull-up resistors, the value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address
transmission, data transfer and STOP signal. The STOP signal should not be confused with the CPU
STOP instruction. The IIC bus system communication is described briefly in the following sections and
illustrated in
8.4.2 START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
Freescale Semiconductor
SDA
SCL
SDA
SCL
Signal
Signal
Start
Start
Figure
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
2
2
8-2.
Calling Address
Calling Address
3
3
4
4
Figure 8-2. IIC Bus Transmission Signals
5
5
6
6
MC68HC908JL16 Data Sheet, Rev. 1.1
7
7
Read/
Write
Read/
Write
LSB
LSB
8
8
Ack
Ack
Bit
Bit
9
9
XX
Repeated
XXX
Signal
Start
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
D6
2
2
New Calling Address
D5
3
3
Data Byte
D4
4
4
D3
5
5
D2
6
6
D1
7
7
Read/
Figure
Write
Functional Description
LSB
LSB
D0
8
8
Ack
No
Bit
Ack
9
No
9
Bit
8-2, a START
Signal
Stop
Signal
Stop
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