MC9S08QG8CDTER Freescale Semiconductor, MC9S08QG8CDTER Datasheet - Page 153
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MC9S08QG8CDTER
Manufacturer Part Number
MC9S08QG8CDTER
Description
IC MCU 8BIT 8K FLASH 16-TSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8CDTER
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
Package
16TSSOP
Family Name
HCS08
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Other names
MC9S08QG8CDTERTR
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Manufacturer
Quantity
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10.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
10.4.1.3
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
10.4.1.4
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
10.4.1.5
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512
Freescale Semiconductor
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CLKS bits are written to 00
IREFS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1
BDM mode is active or LP bit is written to 0
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1
CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is active or LP bit is written to 0.
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
FLL Bypassed External (FBE)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Internal Clock Source (S08ICSV1)
151
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