EZ80F91NA050EG Zilog, EZ80F91NA050EG Datasheet - Page 230
EZ80F91NA050EG
Manufacturer Part Number
EZ80F91NA050EG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3869
EZ80F91NA050EG
EZ80F91NA050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 122. I
PS019215-0910
Code
50h
58h
38h
Note: AAK is an I 2 C control bit that identifies which ACK signal to transmit.
Note:
I
Data byte received,
ACK transmitted
Data byte received,
NACK transmitted
Arbitration lost in
NACK bit
2
C State
2
C Master Receive Status Codes For Data Bytes
address again, this time with the Read bit. The status code then becomes
the responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is
After each data byte is received, the IFLG is set to 1 and one of the status codes listed in
Table 122
When all bytes are received, a NACK must be sent, then the microcontroller must write 1
to the STP bit in the I
the STP bit and returns to an idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I
Read bit after a START condition. The I
set to 1); it then sets the IFLG bit in the I
contains the status code
When I
I
restart. An interrupt is generated and IFLG is set to 1; however, the status does not
change. No second address byte is sent by the master. It is up to the slave to remember it
had been selected prior to the restart.
2
C_SAR register), it transmits an ACK when the first address byte is received after a
2
C enters SLAVE TRANSMIT mode when it receives its own slave address and a
2
C contains a 10-bit slave address (signified by the address range
is loaded into the I
Microcontroller Response
Read data, clear IFLG,
clear AAK = 0*
Or read data, clear IFLG,
set AAK = 1
Read data, set STA,
clear IFLG
Or read data, set STP,
clear IFLG
Or read data, set
STA & STP, clear IFLG
Same as master transmit
2
C_CTL register. The I
A8h
.
2
C_SR register.
2
2
C then transmits an ACK bit (if the AAK bit is
C_CTL register. As a result, the I
2
C then transmits a STOP condition, clears
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Same as master
transmit
2
C Action
10h
Product Specification
instead of
I
2
C Serial I/O Interface
40h
F0h–F7h
2
C_SR register
08h
or
48h
.
in the
. It is
221
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