EZ80F91NA050EG Zilog, EZ80F91NA050EG Datasheet - Page 201
EZ80F91NA050EG
Manufacturer Part Number
EZ80F91NA050EG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3869
EZ80F91NA050EG
EZ80F91NA050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Bit
Position
5
THRE
4
BI
3
FE
2
PE
1
OE
Value
0
1
0
1
0
1
0
1
0
1
Description
Transmit holding register/FIFO is not empty.
Transmit holding register/FIFO. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the UARTx_LSR register. In
case of FIFO only one null character is loaded into the receiver
FIFO with the framing error. The framing error is revealed to
the eZ80
receiver FIFO.
No framing error detected for character at the top of the FIFO.
This bit is reset to 0 when the UARTx_LSR register is read.
Framing error detected for the character at the top of the FIFO.
This bit is set to 1 when the stop bit following the data/parity bit
is logic 0.
The received character at the top of the FIFO does not contain
a parity error. In multidrop mode, this indicates that the
received character is a data byte. This bit is reset to 0 when the
UARTx_LSR register is read.
The received character at the top of the FIFO contains a parity
error. In multidrop mode, this indicates that the received
character is an address byte.
The received character at the top of the FIFO does not contain
an overrun error. This bit is reset to 0 when the UARTx_LSR
register is read.
Overrun error is detected. If the FIFO is not enabled, this
indicates that the data in the receive buffer register was not
read before the next character was transferred into the receiver
buffer register. If the FIFO is enabled, this indicates the FIFO
was already full when an additional character was received by
the receiver shift register. The character in the receiver shift
register is not put into the receiver FIFO.
®
whenever that particular data is read from the
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 MCU
192
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