EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 374

• Manufacturer Part Number: EZ80F91AZA50SG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: 0 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4564

Bus Clock Speed, I2C 233
Bus Mode Controller 70
bus mode state 71, 72, 75
Bus modes 70
bus modes 71, 84, 88
Bus Modes, Switching Between 84
Bus Requests During ZDI Debug Mode 242
bus timing 70
BUSACK 9, 70, 243, 253, 259, 359
BUSACK pin 89, 253, 259
BUSREQ 9, 70, 259
BUSREQ pin 89, 243, 253, 259
Byte Format, I2C 215
C
C source-level debugging 235
capture flag 128
Carrier Sense 311
carrier sense 307
carrier sense window 312
Carrier Sense Window Referencing 312
Carrier Sense, MII 22
Chain Sequence and Length, JTAG Boundary Scan
264
Characteristics, electrical
Charge Pump 269
charge pump 273
Charge Pump, PLL 270
Chip Select Registers 85
Chip Select x Bus Mode Control Register 88
Chip Select x Control Register 87
Chip Select x Lower Bound Register 85
Chip Select x Upper Bound Register 86
Chip Select/Wait State Generator block 6
Chip Selects During Bus Request/Bus Acknowl-
edge Cycles 70
Clear to Send 12, 15, 194
CLK_MUX 273
clock divisor value, 16-bit 182, 208
clock initialization circuitry 262
Clock Peripheral Power-Down Registers 46
clock phase 204
PS027001-0707
Absolute maximum ratings 343
clock phase bit 206
clock polarity bit 206
Clock Synchronization for Handshake 218
Clock Synchronization, I2C 216
Clocking Overview 213
COL 22
Complex triggers 261
CONTINUOUS mode 125
Continuous Mode 123, 126
continuous mode 121, 132, 138, 139
Control Transfers, UART 179
CPHA—see clock phase 204, 205, 210
CPOL—see clock polarity 205, 210
CRC 298, 299, 303, 304, 316
CRS 22, 311
CS0 7, 65, 66, 67, 68
CS1 7, 65, 66, 67, 68
CS2 7, 65, 67, 68
CS3 7, 65, 67, 68
CTS 192, 194
CTS0 12, 200
CTS1 15
Customer Feedback Form 379
D
DATA bus 78
Data Bus 8
data bus 70, 71, 73, 74, 75, 82, 88, 161, 242,
243, 253, 259
Data Carrier Detect 13, 16, 194
Data Set Ready 13, 16, 194
Data Terminal Ready 12, 15, 192
Data Transfer Procedure with SPI configured as a
Slave 208
Data Transfer Procedure with SPI Configured as the
Master 207
data transfer, SPI 211
Data Transfers, UART 179
Data Validity, I2C 214
DATA0 8
DATA1 8
DATA2 8
DATA3 8
Product Specification
eZ80F91 ASSP
366