EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 326
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 199. EMAC PHY Configuration Data Register—Low Byte
PS027001-0707
Bit
Position
[2:0]
CLKS
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_CTLD_L
EMAC PHY Configuration Data Register—Low and High Byte
The Low and High bytes of the EMAC PHY Configuration Data Register represents the
configuration data written to the external PHY. The EMAC_CTLD_H and
EMAC_CTLD_L registers form a 16-bit register. These registers are loaded with data to
be sent via the MDIO pin to the PHY. The PHY is selected by setting the EMAC_FIAD.
The register inside the PHY is selected by setting EMAC_RGAD. See
Table 200
Value
Programmable divisor that produces MDC from SCLK. MDC is the
management data clock pin, which clocks MDIO data to and from the
PHY. its frequency is SCLK divided by the MDC clock divider.
000
001
010
011
100
101
110
111
Value
00h–
FFh
Description
MDC = SCLK ÷ 4.
MDC = SCLK ÷ 4.
MDC = SCLK ÷ 6.
MDC = SCLK ÷ 8.
MDC = SCLK ÷ 10.
MDC = SCLK ÷ 14.
MDC = SCLK ÷ 20.
MDC = SCLK ÷ 28.
R/W
on page 319.
7
0
Description
These bits represent the Low byte of the 2 byte PHY
configuration data value, {EMAC_CTLD_H,
EMAC_CTLD_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
(EMAC_CTLD_L = 003Ch)
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
Table 199 and
eZ80F91 ASSP
318
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