STM32F103VBH6 STMicroelectronics, STM32F103VBH6 Datasheet - Page 42

MCU ARM 128KB FLASH MEM 100-LFBG

STM32F103VBH6

Manufacturer Part Number
STM32F103VBH6
Description
MCU ARM 128KB FLASH MEM 100-LFBG
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103VBH6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN, I2C, SPI, USART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
100
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit x 2, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-6069

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Electrical characteristics
5.3.11
42/67
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size is
either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).
The human body model (HBM) can be simulated. The tests are compliant with JESD22-
A114A standard.
For more details, refer to the application note AN1181.
Table 27.
1. TBD stands for to be determined.
2. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
G
G
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 28.
V
V
Symbol
Symbol
ESD(HBM)
ESD(CDM)
LU
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Static latch-up class
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
ESD absolute maximum ratings
Electrical sensitivities
Parameter
Ratings
T
A
= +105 °C
(1)
Conditions
T
Conditions
A
= +25 °C
Maximum value
2000
TBD
STM32F103xx
II level A
Class
(2)
Unit
V

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