ST72F621J4B1 STMicroelectronics, ST72F621J4B1 Datasheet - Page 47

• Manufacturer Part Number: ST72F621J4B1
• Description: IC MCU 8BIT LS 16K 42-PDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F621J4B1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2110-5

PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generat-
ed if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be re-
set by the user software. This interrupt can be
used as a time base in the application.
Figure 35. External Event Detector Example (3 counts)
f
EXT
COUNTER
=f
COUNTER
OVF
FDh
FEh
ARTARR=FDh
FFh
INTERRUPT
IF OIE=1
Doc ID 6996 Rev 5
FDh
External clock and event detector mode
Using the f
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
is used to select the n
be counted before setting the OVF flag.
When entering HALT mode while f
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Caution: If HALT mode is used in the application,
prior to executing the HALT instruction, the coun-
ter must be disabled by clearing the TCE bit in the
ARTCSR register to avoid spurious counter incre-
ments.
ARTCSR READ
FEh
EXT
n
EVENT
external prescaler input clock, the
FFh
INTERRUPT
IF OIE=1
= 256 - ARTARR
EVENT
FDh
number of events to
ARTCSR READ
EXT
ST7262xxx
is selected,
t
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