ST72F321J9T6 STMicroelectronics, ST72F321J9T6 Datasheet - Page 41

• Manufacturer Part Number: ST72F321J9T6
• Description: MCU 8BIT 60KB FLASH 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20-DVP3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4844

8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(f
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 23. Power Saving Mode Transitions
OSC2
Figure
).
23): SLOW, WAIT (SLOW WAIT), AC-
ACTIVE HALT
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the master clock frequency (f
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 24. SLOW Mode Clock Transitions
CPU
internal clock in the device,
the available supply voltage.
).
ST72321Rx ST72321ARx ST72321Jx
CP1:0
SMS
f
CPU
f
OSC2
f
FREQUENCY
OSC2
00
NEW SLOW
REQUEST
/2
01
CPU
f
OSC2
NORMAL RUN MODE
).
/4
REQUEST
CPU
f
OSC2
41/193
OSC2
) to
)