ST72F325J7T6 STMicroelectronics, ST72F325J7T6 Datasheet - Page 194
![IC MCU 8BIT 48K FLASH 44-LQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F325J7T6
Manufacturer Part Number
ST72F325J7T6
Description
IC MCU 8BIT 48K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F325K6T6.pdf
(197 pages)
Specifications of ST72F325J7T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
A/d Bit Size
10 bit
A/d Channels Available
16
Height
1.4 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3.8 V, 4.5 V
Width
10 mm
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8243
ST72F325J7T6
ST72F325J7T6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F325J7T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST72F325J7T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
KNOWN LIMITATIONS (Cont’d)
15.1.4 SCI Wrong Break duration
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (f
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
15.1.5 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
CPU
=8MHz and SCI-
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.6 TIMD set simultaneously with OC
interrupt
If the 16-bit timer is disabled at the same time the
output compare event occurs then output compare
flag gets locked and cannot be cleared before the
timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the
output compare flag cannot be cleared in the timer
interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the tim-
er. Again while enabling, first enable the timer then
the timer interrupts.
Perform the following to disable the timer:
pare interrupt
Perform the following to enable the timer again:
er
interrupt
15.1.7 I2C Multimaster
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
TACR1 or TBCR1 = 0x00h; // Disable the com-
TACSR | or TBCSR | = 0x40; // Disable the timer
TACSR & or TBCSR &= ~0x40; // Enable the tim-
TACR1 or TBCR1 = 0x40; // Enable the compare
ST72325xx
194/197