ST72F325J7T6 STMicroelectronics, ST72F325J7T6 Datasheet - Page 168
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ST72F325J7T6
Manufacturer Part Number
ST72F325J7T6
Description
IC MCU 8BIT 48K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F325K6T6.pdf
(197 pages)
Specifications of ST72F325J7T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
A/d Bit Size
10 bit
A/d Channels Available
16
Height
1.4 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3.8 V, 4.5 V
Width
10 mm
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8243
ST72F325J7T6
ST72F325J7T6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F325J7T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST72F325J7T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72325xx
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
12.11.2 I
Subject to general operating conditions for V
f
Figure 93. Typical Application with I
Notes:
1. Data based on standard I
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
5. At 4MHz f
168/197
t
CPU
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
t
t
t
su(STA)
h(SDA)
h(STA)
r(SDA)
f(SDA)
SDA
SCK
r(SCL)
f(SCL)
I
C
, and T
2
t
C BUS
f(SDA)
b
2
C - Inter IC Control Interface
CPU
t
A
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
h(STA)
unless otherwise specified.
START
, max.I
4.7kΩ
t
w(SCKH)
t
r(SDA)
2
C speed (400kHz) is not achievable. In this case, max. I
V
2
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7kΩ
V
DD
t
su(SDA)
2
t
r(SCK)
C Bus and Timing Diagram
100Ω
100Ω
t
h(SDA)
t
DD
f(SCK)
DD
,
SDAI
SCLI
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I
requirements of the Standard I
protocol described in the following table.
ST72XXX
Standard mode I
Min
250
0
4.7
4.0
4.7
4.0
4.0
4.7
DD
3)
.
1)
4)
2
Max
1000
C speed will be approximately 260KHz.
300
400
2
1)
C
t
su(STA)
20+0.1C
20+0.1C
t
su(STO)
Min
Fast mode I
100
0
1.3
0.6
0.6
0.6
1.3
0.6
2
2)
C interface meets the
1)
t
w(STO:STA)
STOP
2
b
b
C communication
REPEATED START
Max
900
2
300
300
400
C
5)
3)
1)
START
Unit
pF
μs
ns
μs
μs
μs