ST72F260G1M6 STMicroelectronics, ST72F260G1M6 Datasheet - Page 41

• Manufacturer Part Number: ST72F260G1M6
• Description: MCU 8BIT 4K FLASH ICP 28SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F260G1M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Converters: A/D 6x10b
• Processor Series: ST72F2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-4840

I/O PORTS (Cont’d)
Analog alternate function
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
Figure 28. Interrupt I/O Port State Transitions
floating/pull-up
interrupt
INPUT
01
(reset state)
floating
INPUT
00
Figure
open-drain
OUTPUT
28. Other transitions
10
XX
= DDR, OR
OUTPUT
push-pull
11
9.4 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to
9.5 LOW POWER MODES
9.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
Related Documentation
AN 970: SPI Communication between ST7 and
EEPROM
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
WAIT
HALT
External interrupt on
selected external
event
Mode
Interrupt Event
ST72260Gx, ST72262Gx, ST72264Gx
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Section
Event
Flag
-
Description
Control
Enable
DDRx
13.8.
ORx
Bit
from
Wait
Exit
Yes
41/172
from
Exit
Halt
Yes