LPC2460FBD208,551 NXP Semiconductors, LPC2460FBD208,551 Datasheet - Page 742
LPC2460FBD208,551
Manufacturer Part Number
LPC2460FBD208,551
Description
IC ARM7 MCU ROMLESS 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FBD208,551
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4259
935282455551
LPC2460FBD208-S
935282455551
LPC2460FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP
Quantity:
180
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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5. JTAG function select
6. Register description
7. Block diagram
UM10237_4
User manual
Remark: JTAG access to the LPC2400 is only possible if no code read protection is
selected, see
The JTAG port may be used either for debug or for boundary scan. The state of the
DBGEN pin determines which function is available. When DBGEN = 0, the JTAG port may
be used for boundary scan. When DBGEN = 1, the JTAG port may be used for debug.
The EmbeddedICE logic contains 16 registers as shown in
ARM7TDMI-S debug architecture is described in detail in "ARM7TDMI-S (rev 4) Technical
Reference Manual" (ARM DDI 0234A) published by ARM Limited.
Table 678. EmbeddedICE logic registers
The block diagram of the debug environment is shown below in
Name
Debug Control
Debug Status
Debug Comms Control Register
Debug Comms Data Register
Watchpoint 0 Address Value
Watchpoint 0 Address Mask
Watchpoint 0 Data Value
Watchpoint 0 Data Mask
Watchpoint 0 Control Value
Watchpoint 0 Control Mask
Watchpoint 1 Address Value
Watchpoint 1 Address Mask
Watchpoint 1 Data Value
Watchpoint 1 Data Mask
Watchpoint 1 Control Value
Watchpoint 1 Control Mask
Section
3–5.
Rev. 04 — 26 August 2009
Width
6
5
32
32
32
32
32
32
9
8
32
32
32
32
9
8
Description
Force debug state, disable interrupts
Status of debug
Debug communication control register
Debug communication data register
Holds watchpoint 0 address value
Holds watchpoint 0 address mask
Holds watchpoint 0 data value
Holds watchpoint 0 data mask
Holds watchpoint 0 control value
Holds watchpoint 0 control mask
Holds watchpoint 1 address value
Holds watchpoint 1 address mask
Holds watchpoint 1 data value
Holds watchpoint 1 data mask
Holds watchpoint 1 control value
Holds watchpoint 1 control mask
Chapter 33: LPC24XX EmbeddedICE
Table 33–678
Figure
UM10237
© NXP B.V. 2009. All rights reserved.
33–147.
below. The
Address
00000
00001
00100
00101
01000
01001
01010
01011
01100
01101
10000
10001
10010
10011
10100
10101
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