LPC2460FBD208,551 NXP Semiconductors, LPC2460FBD208,551 Datasheet - Page 540
LPC2460FBD208,551
Manufacturer Part Number
LPC2460FBD208,551
Description
IC ARM7 MCU ROMLESS 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FBD208,551
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4259
935282455551
LPC2460FBD208-S
935282455551
LPC2460FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP
Quantity:
180
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
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NXP Semiconductors
UM10237_4
User manual
5.2.3 SPI format with CPOL=0,CPHA=1
5.2.4 SPI format with CPOL = 1,CPHA = 0
In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data is
enabled onto their respective transmission lines. At the same time, the SCK is enabled
with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in
Fig 98. SPI frame format with CPOL=0 and CPHA=1
•
•
•
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
20–98, which covers both single and continuous transfers.
SSEL
MOSI
MISO
SCK
Rev. 04 — 26 August 2009
Figure
Q
20–99.
MSB
MSB
4 to 16 bits
Chapter 20: LPC24XX SSP interface SSP0/1
LSB
LSB
Q
UM10237
© NXP B.V. 2009. All rights reserved.
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