LPC11C14FBD48/301 NXP Semiconductors, LPC11C14FBD48/301 Datasheet - Page 27

• Manufacturer Part Number: LPC11C14FBD48/301
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC1100r

Specifications of LPC11C14FBD48/301

• Core Size: 32-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: Internal
• Core Processor: ARM Cortex-M0
• Speed: 50MHz
• Connectivity: CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: ARM Cortex-M0
• No. Of I/o's: 40
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Processor Series: LPC11
• Core: ARM Cortex M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 1
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5098

NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.17.6 APB interface
7.17.7 AHBLite
7.17.8 External interrupt inputs
7.18 Emulation and debugging
The C_CAN ISP command handler uses the CANopen protocol and data organization
method. C_CAN ISP commands have the same functionality as UART ISP commands.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 December 2010
Section
7.17.1).
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2010. All rights reserved.
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