P89LPC932A1FDH,529 NXP Semiconductors, P89LPC932A1FDH,529 Datasheet - Page 9

• Manufacturer Part Number: P89LPC932A1FDH,529
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC932A1FDH,529

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• For Use With: OM6292 - DEMO BOARD PCA2125 RTCDB-TSSOP-LPC932 - BOARD FOR LPC932 TSSOP622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9622-1003 - KIT FOR LCD DEMO568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1286-5; 935276132529; P89LPC932A1FDH-S

NXP Semiconductors
Table 2.
P89LPC932A1_3
Product data sheet
Symbol
P1.5/RST
P1.6/OCB
P1.7/OCC
P2.0 to P2.7
P2.0/ICB
P2.1/OCD
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/OCA
Pin description
Pin
TSSOP28,
PLCC28,
DIP28
6
5
4
1
2
13
14
15
16
27
…continued
HVQFN28
2
1
28
25
26
9
10
11
12
23
Type Description
I
I
I/O
O
I/O
O
I/O
I/O
I
I/O
O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until V
power is removed V
operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when V
minimum specified operating voltage.
P1.6 — Port 1 bit 6.
OCB — Output Compare B.
P1.7 — Port 1 bit 7.
OCC — Output Compare C.
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to
and
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0 — Port 2 bit 0.
ICB — Input Capture B.
P2.1 — Port 2 bit 1.
OCD — Output Compare D.
P2.2 — Port 2 bit 2.
MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.3 — Port 2 bit 3.
MISO — When configured as master, this pin is input, when configured as
slave, this pin is output.
P2.4 — Port 2 bit 4.
SS — SPI Slave select.
P2.5 — Port 2 bit 5.
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6 — Port 2 bit 6.
OCA — Output Compare A.
Rev. 03 — 12 March 2007
8-bit microcontroller with accelerated two-clock 80C51 core
Table 8 “Static characteristics”
DD
has reached its specified level. When system
DD
will fall below the minimum specified
Section 7.13.1 “Port configurations”
for details.
P89LPC932A1
© NXP B.V. 2007. All rights reserved.
DD
falls below the
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