P89LPC936FDH,518 NXP Semiconductors, P89LPC936FDH,518 Datasheet - Page 52

• Manufacturer Part Number: P89LPC936FDH,518
• Description: IC 80C51 MCU FLASH 16K 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC936FDH,518

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 21 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit
• On-chip Dac: 2-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4339-2; 935277841518; P89LPC936FDH-T; P89LPC936FDH-T

NXP Semiconductors
9. A/D converter
P89LPC933_934_935_936
Product data sheet
8.28.10 Hardware activation of the boot loader
8.29 User configuration bytes
8.30 User sector security bytes
9.1 General description
9.2 Features and benefits
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC933/934/935/936 User manual for specific
information). This has the same effect as having a non-zero status byte. This allows an
application to be built that will normally execute user code but can be manually forced into
ISP operation. If the factory default setting for the boot vector is changed, it will no longer
point to the factory preprogrammed ISP boot loader code. After programming the flash,
the status byte should be programmed to zero in order to allow execution of the user’s
application code beginning at address 0000H.
Some user-configurable features of the P89LPC933/934/935/936 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the flash byte UCFG1. Please see the
P89LPC933/934/935/936 User manual for additional details.
There are eight User Sector Security Bytes on the P89LPC933/934/935/936 device. Each
byte corresponds to one sector. Please see the P89LPC933/934/935/936 User manual for
additional details.
The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation
analog-to-digital converter modules sharing common control logic. The P89LPC933/934
have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional
DAC module. A block diagram of the A/D converter is shown in
consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input
signal to one of two comparator inputs. The control logic in combination with the SAR
drives a digital-to-analog converter which provides the other input to the comparator. The
output of the comparator is fed to the SAR.
Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation
A/D converters with common control logic (one A/D on the P89LPC933/934).
Four result registers for each A/D.
Six operating modes:
Four conversion start modes:
Fixed channel, single conversion mode.
Fixed channel, continuous conversion mode.
Auto scan, single conversion mode.
Auto scan, continuous conversion mode.
Dual channel, continuous conversion mode.
Single step mode.
Timer triggered start.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC933/934/935/936
Figure
23. Each A/D
© NXP B.V. 2011. All rights reserved.
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