AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 17

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.2
6.2.3
6438ES–ATARM–21-Jun-10
Matrix Slaves
Masters to Slaves Access
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 6-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the DDR multi-port in the DDR multi-port Register (bit DDRMP_DIS) in the
Chip Configuration User Interface.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
• When the DDR multi-port is enabled (DDRMP_DIS=0), the ARM instruction and data are
• When the DDR multi-port is disabled (DDRMP_DIS=1), DDR Port 1 is dedicated to the LCD
respectively connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2
and DDR Port 3.
controller. The remaining masters share DDR Port 2 and DDR Port 3.
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
External Bus Interface
Internal Peripherals
AT91SAM9G45
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