AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 5

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.7
2.7.1
2.8
2.8.1
2.9
2.9.1
2.9.2
2.9.3
6485B–ATARM–28-Sep-09
Pulse Width Modulation Controller (PWM)
Reset Controller (RSTC)
Serial Synchronous Controller (SSC)
PWM: Zero Period
RSTC: NRST Signal, input mode not available at startup
SSC: Clock is Transmitted before the SSC is enabled
SSC: Last RK Clock Cycle when RK Outputs a Clock during data transfer
SSC: First RK Clock Cycle when RK Outputs a Clock during data transfer
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
None
The NRST input mode power-up is not available at reset. The NRST mode is output at power-
up.
None
SSC configuration:
=> the clock is transmitted.
Configure PIO lines for SSC usage after first enabling the SSC.
When the SSC receiver is used with the following conditions:
At the end of the data cycle, the RK pin is set in high impedance which might be seen as an
unexpected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK /(2 x (value +1)).
• Performs a SW reset,
• Program the receive and the transmit frame synchro,
• Program the transmit and the receive clock as continuous (CKO = Continuous Receive and
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
Transmit Clock)
Problem/Fix Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9G45 Errata
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