AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 4

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3.3
2.4
2.4.1
2.5
2.5.1
2.6
2.6.1
4
Image Sensor Interface (ISI)
LCD Controller (LCDC)
High Speed MultiMedia Card Interface (HSMCI)
AT91SAM9G45 Errata
ROM Code: SDCARD
ISI: Codec Path is disabled
LCDC: LCD formula to compute LCD Pixel Clock
HSMCI: R1B Busy Timing
On Reset, the faulty ROM code will copy the fixed ROM code in SRAM and launch it. The con-
nexion through USB to the SAM-BA monitor will work.
Note:
SDCARD boot is not supported.
None
The ISI Codec path is disabled after the capture of each frame and so requires to be enabled
before the capture of the next frame. This may lead to discarding some frames if the frame rate
is high.
None
The LCD formula to compute the LCD pixel clock is system_clock/2*(CLKVAL+1) instead of
system_clock/(CLKVAL+1).
None
Busy line is sampled 2 clock cycles after the command End Bit when the R1B response type is
expected.
This timing is not strictly defined in SD mode.
This timing is defined in MMC Specification V4.3. (R1B busy Timing)
The user must poll the D0 (busy line) through the PIO Controller and wait for a rising edge on
that line.
13. initialize DataFlash, choosing the Enable action in the Scripts rolling menu and press
14. choose Send boot file, press Execute
15. select AT91SAM9G45_RomCode_Replacement.bin binary file and press Open; the
16. close SAM-BA
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem/Fix Workaround
Execute
media is written down
Boot from DataFlash media will no longer be available for other purpose.
6485B–ATARM–28-Sep-09