AT91SAM7L128-CU Atmel, AT91SAM7L128-CU Datasheet - Page 132

• Manufacturer Part Number: AT91SAM7L128-CU
• Description: MCU ARM7 128K HS FLASH 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3
18.3.1
18.3.2
132
Functional Description
AT91SAM7L128/64 Preliminary
Bus Arbiter
Address Decoder
The Memory Controller handles the internal ASB bus and arbitrates the accesses of up to three
masters.
It is made up of:
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the
bus to one of the two masters. The Peripheral DMA Controller has the highest priority, the ARM
processor has the lowest one.
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines three separate areas:
Figure 18-2
Figure 18-2. Memory Areas
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• An Enhanced Embedded Flash Controller
• One 256-Mbyte address space for the internal memories
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 3584 Mbytes representing fourteen 256-Mbyte areas that
return an Abort if accessed
shows the assignment of the 256-Mbyte memory areas.
14 x 256 Mbytes
3,584 Mbytes
256 Mbytes
256 Mbytes
0xF000 0000
0x0000 0000
0xEFFF FFFF
0xFFFF FFFF
0x0FFF FFFF
0x1000 0000
Internal Memories
Peripherals
Undefined
(Abort)
6257A–ATARM–20-Feb-08