ATXMEGA256A3-MH Atmel, ATXMEGA256A3-MH Datasheet - Page 14
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ATXMEGA256A3-MH
Manufacturer Part Number
ATXMEGA256A3-MH
Description
MCU AVR 256K FLASH 1.8V 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATXMEGA64A3-MH.pdf
(134 pages)
Specifications of ATXMEGA256A3-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 2 Channel
On-chip Dac
2 bit, 1 Channel
Package
64QFN EP
Device Core
AVR
Family Name
XMEGA
Maximum Speed
32 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3-MU
ATXMEGA256A3-MU
ATXMEGA256A3-MU
7.7
8068T–AVR–12/10
ATxmega64A3
ATxmega128A3
ATxmega192A3
ATxmega256A3
ATxmega64A3
ATxmega128A3
ATxmega192A3
ATxmega256A3
Devices
Devices
Flash and EEPROM Page Size
128 KB + 8 KB
192 KB + 8 KB
256 KB + 8 KB
64 KB + 4 KB
Flash
Size
EEPROM
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2.
Table 7-3 on page 14
EEEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
Size
2 KB
2 KB
2 KB
4 KB
Page Size
(words)
128
256
256
256
Number of words and Pages in the Flash.
Number of bytes and Pages in the EEPROM.
Page Size
FWORD
(Bytes)
Z[7:1]
Z[8:1]
Z[8:1]
Z[8:1]
shows the Flash Program Memory organization. Flash write and erase
32
32
32
32
shows EEPROM memory organization for the XMEGA A3 devices.
FPAGE
Z[16:8]
Z[17:9]
Z[18:9]
Z[18:9]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
E2BYTE
128K
192K
256K
Size
64K
Application
No of Pages
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[11:5]
E2PAGE
256
256
384
512
Size
4 KB
8 KB
8 KB
8 KB
XMEGA A3
No of Pages
Boot
No of Pages
128
64
64
64
16
16
16
16
14