PIC18LF6621-I/PT Microchip Technology, PIC18LF6621-I/PT Datasheet - Page 27
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6621-I/PT
Manufacturer Part Number
PIC18LF6621-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
Specifications of PIC18LF6621-I/PT
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3.75KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6621-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 27 of 396
- Download datasheet (8Mb)
2.6.1
The system clock source switching is performed under
software control. The system clock switch bits,
SCS1:SCS0 (OSCCON<1:0>), control the clock
switching. When the SCS0 bit is ‘0’, the system clock
source comes from the main oscillator that is selected
by the FOSC configuration bits in the CONFIG1H
Configuration register. When the SCS0 bit is set, the
system clock source will come from the Timer1
oscillator. The SCS0 bit is cleared on all forms of Reset.
When the FOSC bits are programmed for Software PLL
mode, the SCS1 bit can be used to select between
primary oscillator/clock and PLL output. The SCS1 bit
will only have an effect on the system clock if the PLL
is enabled (PLLEN = 1) and locked (LOCK = 1), else it
will be forced cleared. When programmed with
Configuration Controlled PLL, the SCS1 bit will be
forced clear.
REGISTER 2-1:
2005 Microchip Technology Inc.
SYSTEM CLOCK SWITCH BIT
bit 7-4
bit 3
bit 2
bit 1
bit 0
OSCCON: OSCILLATOR CONTROL REGISTER
Unimplemented: Read as ‘0’
LOCK: Phase Lock Loop Lock Status bit
1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and output cannot be used as system clock
PLLEN: Phase Lock Loop Enable bit
1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop
SCS1: System Clock Switch bit 1
When PLLEN and LOCK bits are set:
1 = Use PLL output
0 = Use primary oscillator/clock input pin
When PLLEN or LOCK bit is cleared:
Bit is forced clear.
SCS0: System Clock Switch bit 0
When OSCSEN configuration bit = 0 and T1OSCEN bit = 1:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Legend:
R = Readable bit
-n = Value at POR
bit 7
Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL modes. This
U-0
—
2: The setting of SCS0 = 1 supersedes SCS1 = 1.
bit is writable for ECIO+SPLL and HS+SPLL modes only; forced cleared for all other
oscillator modes.
U-0
—
PIC18F6525/6621/8525/8621
U-0
—
W = Writable bit
‘1’ = Bit is set
(2)
(1)
U-0
—
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
LOCK
The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS0 bit will be ignored (SCS0 bit
forced cleared) and the main oscillator will
continue to be the system clock source.
PLLEN
R/W-0
(1)
x = Bit is unknown
R/W-0
SCS1
DS39612B-page 25
SCS0
R/W-0
bit 0
(2)
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