PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet - Page 342
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6585-I/PT
Manufacturer Part Number
PIC18F6585-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18F6585-I/PT
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6585-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 342 of 496
- Download datasheet (9Mb)
PIC18F6585/8585/6680/8680
23.11 Programming Time Segments
Some requirements for programming of the time
segments:
• Prop_Seg + Phase_Seg 1
• Phase_Seg 2
For example, assume that a 125 kHz CAN baud rate is
desired, using 20 MHz for F
a baud rate prescaler value of 04h gives a T
To obtain a Nominal Bit Rate of 125 kHz, the Nominal
Bit Time must be 8 s or 16 T
Using 1 T
and 7 T
point at 10 T
Phase Segment 2.
By the rules above, the Sync Jump Width could be the
maximum of 4 T
only necessary when the clock generation of the
different nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
23.12 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
23.13 Bit Timing Configuration
The Configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus
interface. These registers can only be modified when
the PIC18F6585/8585/6680/8680 devices are in
Configuration mode.
23.13.1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of T
DS30491C-page 340
Q
Registers
for Phase Segment 1, would place the sample
Q
BRGCON1
for the Sync_Seg, 2 T
Q
after the transition. This leaves 6 T
Q
. However, normally a large SJW is
Sync Jump Width.
Q
.
OSC
Q
Phase_Seg 2
.
. With a T
Q
for the Prop_Seg
OSC
Q
of 500 ns.
of 50 ns,
Q
for
23.13.2
The PRSEG bits set the length of the propagation seg-
ment in terms of T
Phase Segment 1 in T
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times; twice
at T
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a ‘1’, then the length of Phase Segment 2 is
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
information processing time (which is fixed at 2 T
the PIC18F6585/8585/6680/8680).
23.13.3
The PHSEG2<2:0> bits set the length (in T
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
23.14 Error Detection
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
23.14.1
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
Q
/2 before the sample point and once at the normal
BRGCON2
BRGCON3
CRC ERROR
Q
. The SEG1PH bits set the length of
2004 Microchip Technology Inc.
Q
. The SAM bit controls how
Q
) of Phase
Q
for
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