PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet - Page 248
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6585-I/PT
Manufacturer Part Number
PIC18F6585-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18F6585-I/PT
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6585-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 248 of 496
- Download datasheet (9Mb)
PIC18F6585/8585/6680/8680
18.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RC7/RX/DT pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a synchronous master reception:
1.
2.
FIGURE 18-12:
TABLE 18-8:
DS30491C-page 246
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
RC7/RX/DT pin
RC7/TX/CK pin
RC7/TX/CK pin
Name
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Note:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
USART Receive Register
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
USART SYNCHRONOUS MASTER
RECEPTION
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
Q2
—
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 0
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
bit 2
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
BRGH
FERR
Bit 2
—
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
bit 5
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
bit 6
2004 Microchip Technology Inc.
0000 0000
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7
Q1 Q2 Q3 Q4
0000 0000
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
Value on
all other
Resets
‘0’
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