DSPIC30F5013-30I/PT Microchip Technology, DSPIC30F5013-30I/PT Datasheet - Page 216
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DSPIC30F5013-30I/PT
Manufacturer Part Number
DSPIC30F5013-30I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5011-20IPT.pdf
(220 pages)
2.DSPIC30F5011-20IPT.pdf
(16 pages)
3.DSPIC30F5011-20IPT.pdf
(6 pages)
4.DSPIC30F5011-20IPT.pdf
(14 pages)
5.DSPIC30F5011-20IPT.pdf
(26 pages)
6.DSPIC30F5011-20IPTG.pdf
(222 pages)
Specifications of DSPIC30F5013-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
66KB
Supply Voltage Range
2.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F501330IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5013-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F5011/5013
Output Compare Interrupts ................................................. 87
Output Compare Module..................................................... 85
Output Compare Operation During CPU Idle Mode............ 87
Output Compare Sleep Mode Operation............................. 87
P
Packaging Information ...................................................... 207
Peripheral Module Disable (PMD) Registers .................... 152
PICSTART Plus Development Programmer ..................... 166
Pinout Descriptions ............................................................. 12
PLL Clock Timing Specifications....................................... 178
POR. See Power-on Reset.
Port Write/Read Example.................................................... 62
PORTA
PORTB
PORTC
PORTD
PORTF
PORTG
Power Saving Modes ........................................................ 150
Power-Down Current (I
Power-up Timer
Program Address Space ..................................................... 25
Program and EEPROM Characteristics ............................ 175
Program Counter................................................................. 16
Programmable................................................................... 139
Programmer’s Model........................................................... 16
Programming Operations .................................................... 51
DS70116H-page 216
Register Map............................................................... 88
Timing Characteristics .............................................. 187
Timing Requirements ................................................ 187
Marking ..................................................................... 207
Register Map for dsPIC30F5013 ................................ 63
Register Map for dsPIC30F5011/5013 ....................... 63
Register Map for dsPIC30F5011 ................................ 63
Register Map for dsPIC30F5013 ................................ 63
Register Map for dsPIC30F5011 ................................ 64
Register Map for dsPIC30F5013 ................................ 64
Register Map for dsPIC30F5011 ................................ 64
Register Map for dsPIC30F5013 ................................ 65
Register Map for dsPIC30F5011/5013 ....................... 65
Idle ............................................................................ 151
Sleep ......................................................................... 150
Sleep and Idle ........................................................... 139
Timing Characteristics .............................................. 181
Timing Requirements ................................................ 182
Construction ................................................................ 26
Data Access from Program Memory
Data Access From Program Memory
Data Access from, Address Generation...................... 26
Data Space Window into Operation ............................ 29
Data Table Access (LS Word) .................................... 27
Data Table Access (MS Byte) ..................................... 28
Memory Map ............................................................... 25
Table Instructions
Diagram ...................................................................... 17
Algorithm for Program Flash ....................................... 51
Erasing a Row of Program Memory ............................ 51
Initiating the Programming Sequence ......................... 52
Loading Write Latches ................................................ 52
Using Program Space Visibility........................... 28
Using Table Instructions ..................................... 27
TBLRDH.............................................................. 27
TBLRDL .............................................................. 27
TBLWTH ............................................................. 27
TBLWTL.............................................................. 27
PD
) ................................................ 171
Protection Against Accidental Writes to OSCCON ........... 144
R
Reader Response............................................................. 220
Reset ........................................................................ 139, 145
Reset Sequence ................................................................. 39
Reset Sources
Reset Timing Characteristics............................................ 181
Reset Timing Requirements ............................................. 182
Run-Time Self-Programming (RTSP) ................................. 49
S
Simple Capture Event Mode............................................... 81
Simple OC/PWM Mode Timing Requirements ................. 188
Simple Output Compare Match Mode ................................ 86
Simple PWM Mode ............................................................. 86
Software Simulator (MPLAB SIM) .................................... 164
Software Stack Pointer, Frame Pointer .............................. 16
SPI Module ......................................................................... 89
Status Bits, Their Significance and the Initialization
Status Bits, Their Significance and the Initialization
Status Register ................................................................... 16
Symbols Used in Opcode Descriptions ............................ 156
System Integration............................................................ 139
BOR, Programmable ................................................ 147
Brown-out Reset (BOR)............................................ 139
Oscillator Start-up Timer (OST) ................................ 139
POR
POR (Power-on Reset)............................................. 145
Power-on Reset (POR)............................................. 139
Power-up Timer (PWRT) .......................................... 139
Reset Sources ............................................................ 39
Brown-out Reset (BOR).............................................. 39
Illegal Instruction Trap ................................................ 39
Trap Lockout............................................................... 39
Uninitialized W Register Trap ..................................... 39
Watchdog Time-out .................................................... 39
Buffer Operation ......................................................... 82
Hall Sensor Mode ....................................................... 82
Prescaler .................................................................... 81
Timer2 and Timer3 Selection Mode............................ 82
Input Pin Fault Protection ........................................... 86
Period ......................................................................... 87
CALL Stack Frame ..................................................... 33
Framed SPI Support ................................................... 89
Operating Function Description .................................. 89
Operation During CPU Idle Mode ............................... 91
Operation During CPU Sleep Mode............................ 91
SDOx Disable ............................................................. 89
Slave Select Synchronization ..................................... 91
SPI1 Register Map...................................................... 92
SPI2 Register Map...................................................... 92
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 89
Condition for RCON Register, Case 1 ...................... 148
Condition for RCON Register, Case 2 ...................... 149
Operating without FSCM and PWRT................ 147
With Long Crystal Start-up Time ...................... 147
Master Mode (CKE = 0).................................... 192
Master Mode (CKE = 1).................................... 193
Slave Mode (CKE = 1).............................. 194, 195
Master Mode (CKE = 0).................................... 192
Master Mode (CKE = 1).................................... 193
Slave Mode (CKE = 0)...................................... 194
Slave Mode (CKE = 1)...................................... 196
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