DSPIC33FJ256GP510A-I/PF Microchip Technology, DSPIC33FJ256GP510A-I/PF Datasheet - Page 251

• Manufacturer Part Number: DSPIC33FJ256GP510A-I/PF
• Description: IC MCU 16BIT 256KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510A-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.0
dsPIC33FJXXXGPX06A/X08A/X10A devices include
the following features intended to maximize application
flexibility and reliability, and minimize cost through elim-
ination of external components:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 22-1:
© 2011 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Address
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
Note 1: This data sheet summarizes the features
2: When read, this bit returns the current programmed value.
3: This bit is unimplemented on dsPIC33FJ64GPX06A/X08A/X10A and dsPIC33FJ128GPX06A/X08A/X10A
4: These bits are reserved and always read as ‘1’.
2: Some registers and associated bits
SPECIAL FEATURES
devices and reads as ‘0’.
of the dsPIC33FJXXXGPX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
23.
(DS70199), Section 24. “Programming
and Diagnostics” (DS70207), and Sec-
tion
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Name
DEVICE CONFIGURATION REGISTER MAP
25.
“CodeGuard™
FWDTEN
dsPIC33FJXXXGPX06A/X08A/X10A
“Device
IESO
Bit 7
—
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
Reserved
Reserved
Configuration”
WINDIS
Bit 6
(1)
—
Security”
(2)
(4)
PLLKEN
JTAGEN
in
Bit 5
—
—
—
—
—
(3)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
22.1
dsPIC33FJXXXGPX06A/X08A/X10A devices provide
nonvolatile
configuration bits. Refer to Section 25. “Device Con-
figuration” (DS70194) of the “dsPIC33F/PIC24H
Family Reference Manual”, for more information on this
implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table
The individual Configuration bit descriptions for the
Configuration registers are shown in
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
Bit 4
—
—
—
—
—
—
—
22-1.
Configuration Bits
memory
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
implementation
GSS1
Bit 2
—
FPWRT<2:0>
FNOSC<2:0>
DS70593C-page 251
GSS0
Table
Bit 1
ICS<1:0>
for
22-2.
GWRP
BWRP
SWRP
Bit 0
device