DSPIC33FJ256GP510A-I/PF Microchip Technology, DSPIC33FJ256GP510A-I/PF Datasheet - Page 159

• Manufacturer Part Number: DSPIC33FJ256GP510A-I/PF
• Description: IC MCU 16BIT 256KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510A-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.0
The dsPIC33FJXXXGPX06A/X08A/X10A devices pro-
vide the ability to manage power consumption by selec-
tively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked con-
stitutes
dsPIC33FJXXXGPX06A/X08A/X10A
manage power consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
dsPIC33FJXXXGPX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not
high-precision oscillators by simply changing the
NOSC bits (OSCCON<10:8>). The process of
changing a system clock during operation, as well as
limitations to the process, are discussed in more detail
in
EXAMPLE 10-1:
© 2011 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Section 9.0 “Oscillator
Note 1: This data sheet summarizes the features
locked,
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
of the dsPIC33FJXXXGPX06A/X08A/
X10A family of devices. However, it is not
intended
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog Timer and
Power-Saving Modes” (DS70196) in
the
Reference Manual”, which is available
from
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
lower
users
the
“dsPIC33F/PIC24H
PWRSAV INSTRUCTION SYNTAX
can
to
dsPIC33FJXXXGPX06A/X08A/X10A
Configuration”.
Microchip
be
; Put the device into SLEEP mode
; Put the device into IDLE mode
consumed
choose
a
comprehensive
low-power
devices
web
Family
power.
site
can
in
or
10.2
dsPIC33FJXXXGPX06A/X08A/X10A devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembly syntax of the PWRSAV
instruction is shown in
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current
during Sleep mode since the system clock source
is disabled
the WDT is enabled
prior to entering Sleep mode
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE
constants defined in the assembler
include file for the selected device.
Example
and
10-1.
IDLE_MODE
DS70593C-page 159
are