DSPIC33FJ256GP510-I/PF Microchip Technology, DSPIC33FJ256GP510-I/PF Datasheet - Page 7

• Manufacturer Part Number: DSPIC33FJ256GP510-I/PF
• Description: IC DSPIC MCU/DSP 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2. Module: ADC
TABLE 3:
© 2010 Microchip Technology Inc.
Param No.
AD21aa
AD22aa
AD23aa
AD24aa
AD20a
AD21a
AD22a
AD23a
AD24a
AD33a
AD34a
AD56a
AD57a
AD17
When the ADC module is configured for 12-bit
operation, the specifications in the data sheets are
not met.
Work around
Implement the ADC module as an 11-bit ADC with
a maximum conversion rate of 300 ksps.
1. The specifications in Table 3 reflect 11-bit ADC
2. When used as a 10-bit ADC, the INL is <±2
Affected Silicon Revisions
A2
X
operation.
recommended as 200 ohms and sample time
is recommended as 3 T
compatibility
modules. Missing codes are possible every 2
codes.
Least Significant Bytes (LSBs), and DNL
is <±1 LSB with no missing codes. Maximum
conversion rate is 300 ksps.
A3
X
ADC PERFORMANCE (11-BIT OPERATION)
Symbol
TSAMP
GERR
GERR
FNYQ
ENOB
EOFF
EOFF
FCNV
DNL
DNL
A4
RIN
INL
INL
X
Nr
RIN
on
ADC Accuracy – Measurements taken with External V
ADC Accuracy – Measurements taken with Internal V
source
future
Min.
-1.5
-1.5
9.5
—
—
—
—
—
-2
-2
1
1
5
3
enhanced
AD
impedance
to ensure
Dynamic Performance
ADC Conversion Rate
Typical
ADC
12 bits
3 T
9.6
10
—
—
—
—
—
—
—
5
3
6
is
7
AD
Max.
10.4
200
150
300
10
20
15
—
—
2
1
6
2
1
REF
REF
Units
Ohm
ksps
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Bits
kHz
Bits
+/V
+/V
—
REF
REF
-
-
Conditions
DS80446D-page 7
12-bit
—
—
—
—
—
—
—
—
—
—
—
—
—