DSPIC33FJ256GP510-I/PF Microchip Technology, DSPIC33FJ256GP510-I/PF Datasheet - Page 22

• Manufacturer Part Number: DSPIC33FJ256GP510-I/PF
• Description: IC DSPIC MCU/DSP 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

54. Module: ECAN
55. Module: I
DS80446D-page 22
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine may not clear
the flag. The WAKIF bit being set will not cause
repetitive Interrupt Service Routine execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
When the I
after the ACKSTAT bit is set when receiving a
NACK from the slave, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
2
2
C module is operating in Master mode,
C
A4
A4
X
X
56. Module: SPI
57. Module: DCI
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data. Applications which use SPI
with DMA will not be affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI Clock before writing to the
SPIxBUF register.
Alternately, do one of the following:
a)
b)
c)
d)
Affected Silicon Revisions
If the value of BLEN in DCICON2 is greater than
‘0’, the DCI module allows the data in registers
TXBUF1, TXBUF and TXBUF3 to be overwritten
while TXBUF0 is being transmitted. This results in
the loss of the original contents of TXBUF1,
TXBUF2 and TXBUF3. In addition, subsequent
TXBUF1-3 register values will not be synchronized
with TXBUF0.
Work around
The application software must introduce a delay at
the start of the DCI Interrupt Service Routine. This
delay must be long enough for the DCI module to
complete transmission of TXBUF0. New values
can then be written to all of the transmit registers.
Affected Silicon Revisions
A2
A2
X
X
Poll the RBF bit and wait for it to get set
before writing to the SPIxBUF register
Poll the SPI Interrupt flag and wait for it to
get set before writing to the SPIxBUF
register
Use an SPI Interrupt Service Routine (ISR)
Use DMA
A3
A3
X
X
A4
A4
X
X
© 2010 Microchip Technology Inc.