DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 212

• Manufacturer Part Number: DSPIC30F5011-20I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20I/PTG; DSPIC30F501120/PT; DSPIC30F501120IPT; DSPIC30F501120IPT

dsPIC30F5011/5013
Data Address Space ........................................................... 28
Data Converter Interface (DCI) Module ............................ 117
Data EEPROM Memory ...................................................... 53
DC Characteristics ............................................................ 164
DCI Module
DS70116J-page 212
Overflow and Saturation ............................................. 20
Round Logic ................................................................ 21
Write Back................................................................... 21
Alignment .................................................................... 30
Alignment (Figure) ...................................................... 30
Effect of Invalid Memory Accesses (Table)................. 30
MCU and DSP (MAC Class) Instructions Example..... 29
Memory Map ............................................................... 28
Near Data Space ........................................................ 31
Software Stack ............................................................ 31
Spaces ........................................................................ 30
Width ........................................................................... 30
Erasing ........................................................................ 54
Erasing, Block ............................................................. 54
Erasing, Word ............................................................. 54
Protection Against Spurious Write .............................. 56
Reading....................................................................... 53
Write Verify ................................................................. 56
Writing ......................................................................... 55
Writing, Block .............................................................. 56
Writing, Word .............................................................. 55
BOR .......................................................................... 172
Brown-out Reset ....................................................... 171
I/O Pin Output Specifications .................................... 170
Idle Current (I
Low-Voltage Detect................................................... 170
LVDL ......................................................................... 171
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 172
Temperature and Voltage Specifications .................. 165
Bit Clock Generator................................................... 121
Buffer Alignment with Data Frames .......................... 123
Buffer Control ............................................................ 117
Buffer Data Alignment ............................................... 117
Buffer Length Control ................................................ 123
COFS Pin.................................................................. 117
CSCK Pin.................................................................. 117
CSDI Pin ................................................................... 117
CSDO Mode Bit ........................................................ 124
CSDO Pin ................................................................. 117
Data Justification Control Bit ..................................... 122
Device Frequencies for Common Codec CSCK Frequen-
Digital Loopback Mode ............................................. 124
Enable....................................................................... 119
Frame Sync Generator ............................................. 119
Frame Sync Mode Control Bits ................................. 119
I/O Pins ..................................................................... 117
Interrupts ................................................................... 124
Introduction ............................................................... 117
Master Frame Sync Operation .................................. 119
Operation .................................................................. 119
Operation During CPU Idle Mode ............................. 124
Operation During CPU Sleep Mode .......................... 124
Receive Slot Enable Bits........................................... 122
Receive Status Bits ................................................... 123
Register Map............................................................. 126
Sample Clock Edge Control Bit................................. 122
Slave Frame Sync Operation .................................... 119
cies (Table) ....................................................... 121
IDLE
) .................................................... 167
DD
)............................................. 165
PD
) ........................................ 168
Development Support ....................................................... 159
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART .......................................................... 101
Divide Support .................................................................... 18
DSP Engine ........................................................................ 18
Dual Output Compare Match Mode .................................... 82
E
Electrical Characteristics .................................................. 163
Enabling and Setting Up UART
Enabling the UART ........................................................... 101
Equations
Errata .................................................................................... 7
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 174
External Interrupt Requests ................................................ 39
F
Fast Context Saving ........................................................... 39
Flash Program Memory ...................................................... 47
I
I/O Ports.............................................................................. 57
Slot Enable Bits Operation with Frame Sync............ 122
Slot Status Bits ......................................................... 124
Synchronous Data Transfers .................................... 122
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 122
Transmit Status Bits.................................................. 123
Transmit/Receive Shift Register ............................... 117
Underflow Mode Control Bit...................................... 124
Word Size Selection Bits .......................................... 119
Register Map ............................................................ 150
FBORPOR ................................................................ 148
FBS........................................................................... 148
FGS .......................................................................... 148
FOSC........................................................................ 148
FSS........................................................................... 148
FWDT ....................................................................... 148
Instructions (Table) ..................................................... 18
Multiplier ..................................................................... 20
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
AC............................................................................. 173
DC ............................................................................ 164
Setting Up Data, Parity and Stop Bit Selections ....... 101
ADC Conversion Clock ............................................. 129
Baud Rate................................................................. 103
Bit Clock Frequency.................................................. 121
COFSG Period.......................................................... 119
Serial Clock Rate ........................................................ 96
Time Quantum for Clock Generation ........................ 113
Trap Sources .............................................................. 37
Type A, B and C Timer ............................................. 181
Type A Timer ............................................................ 181
Type B Timer ............................................................ 182
Type C Timer ............................................................ 182
Parallel (PIO) .............................................................. 57
AC-Link Mode................................................... 188
Multichannel, I
AC-Link Mode................................................... 188
Multichannel, I
2
2
S Modes................................... 186
S Modes................................... 187
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