DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 111
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DSPIC30F5011-20I/PT
Manufacturer Part Number
DSPIC30F5011-20I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5011-20IPT.pdf
(220 pages)
2.DSPIC30F5011-20IPT.pdf
(16 pages)
3.DSPIC30F5011-20IPT.pdf
(6 pages)
4.DSPIC30F5011-20IPT.pdf
(14 pages)
5.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5011-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5011-20I/PTG
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
DSPIC30F501120/PT
DSPIC30F501120IPT
DSPIC30F501120IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F5011-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
• Receive Error Interrupts:
17.5
17.5.1
The CAN module has three transmit buffers. Each of
the three buffers occupies 14 bytes of data. Eight of the
bytes are the maximum 8 bytes of the transmitted mes-
sage. Five bytes hold the standard and extended
identifiers and other message arbitration information.
17.5.2
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are
4 levels
(CiTXnCON<1:0>, where n = 0, 1 or 2 represents a par-
ticular transmit buffer) for a particular message buffer is
set to ‘11’, that buffer has the highest priority. If
TXPRI<1:0> for a particular message buffer is set to
‘10’ or ‘01’, that buffer has an intermediate priority. If
TXPRI<1:0> for a particular message buffer is ‘00’, that
buffer has the lowest priority.
17.5.3
To initiate transmission of the message, the TXREQ bit
(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the Start-of-Frame (SOF), ensuring that if
the priority was changed, it is resolved correctly before the
SOF occurs. When TXREQ is set, the TXABT
(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
(CiTXnCON<4>) flag bits are automatically cleared.
© 2011 Microchip Technology Inc.
- Invalid Message Received:
- Receiver Overrun:
- Receiver Warning:
- Receiver Error Passive:
A receive error interrupt will be indicated by the
ERRIF bit. This bit shows that an error condition
occurred. The source of the error can be deter-
mined by checking the bits in the CAN Interrupt
Status register, CiINTF.
If any type of error occurred during reception of
the last message, an error will be indicated by
the IVRIF bit.
The RXnOVR bit indicates that an overrun
condition occurred.
The RXWAR bit indicates that the receive error
counter (RERRCNT<7:0>) has reached the
warning limit of 96.
The RXEP bit indicates that the receive error
counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
Message Transmission
of
TRANSMIT BUFFERS
TRANSMIT MESSAGE PRIORITY
TRANSMISSION SEQUENCE
transmit
priority.
If
TXPRI<1:0>
Setting TXREQ bit simply flags a message buffer as
enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determined to have the highest priority.
If the transmission completes successfully on the first
attempt, the TXREQ bit is cleared automatically, and an
interrupt is generated if TXIE was set.
If the message transmission fails, one of the error con-
dition flags will be set, and the TXREQ bit will remain
set indicating that the message is still pending for trans-
mission. If the message encountered an error condition
during the transmission attempt, the TXERR bit will be
set, and the error condition may cause an interrupt. If
the message loses arbitration during the transmission
attempt, the TXLARB bit is set. No interrupt is
generated to signal the loss of arbitration.
17.5.4
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer. Set-
ting the ABAT bit (CiCTRL<12>) will request an abort of
all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
17.5.5
The CAN module will detect the following transmission
errors:
• Acknowledge Error
• Form Error
• Bit Error
These transmission errors will not necessarily generate
an interrupt but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF bit (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Error Flag register
is set.
dsPIC30F5011/5013
ABORTING MESSAGE
TRANSMISSION
TRANSMISSION ERRORS
DS70116J-page 111