AT89C5130A-S3SUM Atmel, AT89C5130A-S3SUM Datasheet - Page 129
![IC 8051 MCU FLASH 16K USB 52PLCC](/photos/12/13/121324/453-52-plcc_sml.jpg)
AT89C5130A-S3SUM
Manufacturer Part Number
AT89C5130A-S3SUM
Description
IC 8051 MCU FLASH 16K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5130A-S3SUM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
2-Wire, EUART, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
34
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Minimum Operating Temperature
- 40 C
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
AT89C5130A-S3SIM
AT89C5130A-S3SIM
AT89C5130A-S3SIM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
21.4.4
4337K–USB–04/08
Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEP-
STAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning the endpoint. The FIFO banks are automatically switched, and the firmware can
immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks
are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-
ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
will answer a NAK handshake for each IN requests concerning this bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before
setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at
the same time the TXCMPL bit for bank 0 and the bank 1.
HOST
IN
IN
IN
IN
ACK
ACK
ACK
DATA0 (n Bytes)
DATA1 (m Bytes)
DATA0 (p Bytes)
NACK
UFI
TXCMPL
TXCMPL
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte n
Endpoint FIFO Bank 1 - Write Byte 1
Endpoint FIFO Bank 1 - Write Byte 2
Endpoint FIFO Bank 1 - Write Byte m
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte p
Endpoint FIFO Bank 1 - Write Byte 1
AT89C5130A/31A-M
C51
Clear TXCMPL
Clear TXCMPL
Set TXRDY
Set TXRDY
Set TXRDY
129