AT89C5130A-S3SUM Atmel, AT89C5130A-S3SUM Datasheet - Page 101
![IC 8051 MCU FLASH 16K USB 52PLCC](/photos/12/13/121324/453-52-plcc_sml.jpg)
AT89C5130A-S3SUM
Manufacturer Part Number
AT89C5130A-S3SUM
Description
IC 8051 MCU FLASH 16K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5130A-S3SUM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
2-Wire, EUART, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
34
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Minimum Operating Temperature
- 40 C
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
AT89C5130A-S3SIM
AT89C5130A-S3SIM
AT89C5130A-S3SIM
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19.3.5.3
4337K–USB–04/08
Serial Peripheral Data Register (SPDAT)
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register
ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 19-5.
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-
going exchange. However, special care should be taken when writing to them while a transmis-
sion is on-going:
Bit Number
• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow
R7
4
3
2
1
0
7
Mnemonic
SPDAT Register
MODF
Bit
R6
-
-
-
-
6
Description
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been
approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
R5
5
(Table
R4
4
19-5) is a read/write buffer for the receive data regis-
R3
3
AT89C5130A/31A-M
R2
2
R1
1
R0
0
101
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