AT89C51CC03U-RDRIM Atmel, AT89C51CC03U-RDRIM Datasheet - Page 4

• Manufacturer Part Number: AT89C51CC03U-RDRIM
• Description: IC 8051 MCU FLASH 64K 64VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC03U-RDRIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT89C51CC03URDRTR

Mapping and Default
Value of Hardware
Security Byte
Security
4
AT89C51CC03 CAN Bootloader
The 4 MSB of the Hardware Byte can be read/written by software (this area is called Fuse bits).
The 4 LSB can only be read by software and written by hardware in parallel mode (with parallel
programmer devices).
Note:
The bootloader has Software Security Byte (SSB) to protect itself from user access or ISP
access.
The Software Security Byte (SSB) protects from ISP accesses. The command "Program Soft-
ware Security Bit" can only write a higher priority level. There are three levels of security:
•
•
•
Only a full chip erase command can reset the software security bits.
Level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
Level 1: WRITE_SECURITY (FEh)
In this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootloader returns ID_ERROR message.
From level 1, one can write only level 2.
Level 2: RD_WR_SECURITY (FCh)
Level 2 forbids all read and write accesses to/from the Flash memory.
The Bootloader returns ID_ERROR message.
U: Unprogram = 1
P: Program = 0
Flash/EEPROM
Fuse bit
BSB & SBV & EB Any access allowed
SSB
Manufacturer info Read only access allowed
Bootloader info
Erase block
Full chip erase
Blank Check
Bit Position
7
6
5
4
3
2
1
0
X2B
BLJB
reserved
reserved
reserved
LB2
LB1
LB0
Mnemonic
Level 0
Any access allowed
Any access allowed
Any access allowed
Read only access allowed
Allowed
Allowed
Allowed
Default Value
U
U
U
U
U
U
P
P
Description
To start in x1 mode
To map the boot area in code area between F800h-FFFFh
To lock the chip (see datasheet)
Level 1
Read only access allowed
Read only access allowed
Read only access allowed
Write level2 allowed
Read only access allowed
Read only access allowed
Not allowed
Allowed
Allowed
Level 2
All access not allowed
All access not allowed
All access not allowed
Read only access allowed
All access not allowed
All access not allowed
Not allowed
Allowed
Allowed
4251B–CAN–03/08